期刊文献+

5管SRAM单元的抗辐射性能研究 被引量:1

Research on the Radiation Robustness of 5T SRAM Cell
下载PDF
导出
摘要 利用3DTCAD仿真,在45nm体硅工艺下,对5管SRAM单元和传统6管SRAM单元的抗辐射性能进行了对比研究。结果表明,5管SRAM单元的敏感面积更小,由该单元构成的SRAM阵列更难发生多位翻转。提出了一种带额外保护环的5管SRAM单元抗辐射加固策略,这种加固策略没有面积开销,模拟结果证实了该加固策略的有效性。 Using 3D TCAD simulation, the radiation robustness of 5T SRAM cell was compared with that of the conventional 6T SRAM cell in 45 nm bulk CMOS process. The research indicated that the 5T SRAM cell had a smaller sensitive volume. Multiple cells upset (MCU) was also less likely to happen in 5T SRAM. Moreover, a kind of 5T SRAM with additional guard ring hardening scheme was proposed. This hardening scheme could make full use of the chip area and its effectiveness was verified by the simulation results.
机构地区 国防科技大学
出处 《微电子学》 CAS CSCD 北大核心 2015年第6期796-799,共4页 Microelectronics
基金 国家自然科学基金资助项目(61376109)
关键词 5管SRAM单元 单粒子翻转 多位翻转 电荷收集 5T SRAM cell Single event upset Multiple cells upset Charge collection
  • 相关文献

参考文献5

  • 1DODD P E, MASSENGILL L W. Basic mechanisms and modeling of single-event upset in digital microelectronics [J-]. IEEE Trans Nucl Sci, 2003, 50 (3) : 583-602.
  • 2BAUMANN R. The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction[C] /// IEDM. San Francisco, CA, USA. 2002: 329-332.
  • 3NALAM S, CALHOUN B H. 5T SRAM with asymmetric sizing for improved read stability [J]. IEEE J Sol Sta Cite, 2011, 46(10).. 2431-2442.
  • 4MORITA Y, FUJIWARA H, NOGUCHI H, et al. AVta-variation-tolerant SRAM with 0.3 V minimum operation voltage for memory-rich SOC under DVS environment [C] // Syrup VLSI Circ. Honolulu, HI, USA. 2006: 13-14.
  • 5NARASIMHAM B, GAMBLES J W, SHULER R L, et al. Quantifying the effect of guard rings and guard drains in mitigating charge collection and charge spread [J]. IEEE Trans Nuel Sci, 2008, 55(6) : 3456-3460.

同被引文献9

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部