部分耗尽SOI器件背栅界面陷阱密度的提取

Extraction of Back Channel Interface Traps Density for PD SOI Device

利用基于复合理论的直流电流电压法,提取SOI器件背栅界面陷阱密度。给出了具体的测试原理,以0.13μm SOI工艺制造的部分耗尽NMOS和PMOS器件为测试对象,分别对两种器件的背界面复合电流进行测试。将实验得到的界面复合电流值与理论公式作最小二乘拟合,不仅可以获得背界面陷阱密度,还可以得到界面陷阱密度所在的等效能级。结果表明,采用智能剥离技术制备的SOI器件的背界面陷阱密度量级均为1010cm-2,但NMOS器件的背界面陷阱密度略大于PMOS器件,并给出了界面陷阱密度所在的等效能级。

The DC current voltage method based on recombination theory could be used for extracting the back channel interface traps density of SOI device. The concrete measurement mechanism was presented, and it was applied to measure the back channel interface recombination currents in partially depleted SOI NMOSFET and PMOSFET which were fabricated in 0.13 μm process. The interface recombination currents obtained could be used to fit the theoretical equation with least-squares optimization, so both the interface trap density and its equivalent energy level could be acquired. The results indicated that the back channel interface trap density of both SOI NMOSFET and PMOSFET which adopt SMART-CUT technique were about 10^10 cm-2, but the interface trap density of NMOSFET was larger than PMOSFET＇s. The corresponding interface trap density equivalent energy level was also given.