一种自偏置全集成的低功耗带隙基准电路设计

Design of a Fully Integrated Bandgap Reference Circuit with Self-Bias and Low-Power Consumption

为满足可穿戴集成电路的低功耗应用需求,设计了一种自偏置全集成的带隙基准电压电路。该电路采用纯CMOS结构,利用金属氧化物半导体场效应晶体管(MOSFET)的阈值电压与温度呈反比、热电压与温度呈正比的关系,通过电路结构设计与晶体管尺寸优化,获得一个与温度无关的基准电压。电路中的MOSFET偏置于工作电流极低的亚阈值区,从而有效降低了整个带隙基准电路的功耗。采用CSMC 0.18μm CMOS工艺,在Aether软件环境下完成了电路的仿真和版图设计。后仿真结果表明,室温下,电源电压为3.3 V时,电路总电流为81.2 nA,输出基准电压为1.03 V,启动时间约为0.48μs,功耗约为268 nW,在-40~125℃的范围内温度漂移系数为3.2×10-5/℃。流片后在片测试结果表明,当电源电压在1.6~3.3 V之间变化时,电路输出电压稳定。

A self-biased and fully integrated bandgap reference circuit was designed to meet the needs of low-power applications for wearable integrated circuits.The designed circuit adopted a pure CMOS structure.According to the threshold voltage of the metal oxide semiconductor field effect transistor(MOSFET)inversely proportional to temperature,while its hot voltage proportional to temperature,a temperature-independent reference voltage was obtained through the proper circuit structure and the transistor size optimization.The MOSFET operated in the subthreshold region with a very low working current,the power consumption of the whole designed bandgap reference circuit was effectively reduced.With CSMC 0.18μm CMOS process,the simulation and the layout design of the designed circuit were completed in Aether software.The post-simulation results show that at room temperature,when the power supply voltage is 3.3 V,the total current of the circuit is 81.2 nA,the output reference voltage is 1.03 V,the startup time is about 0.48μs,the power consumption is about 268 nW and the temperature drift coefficient is 3.2×10-5/℃in the range of-40~125℃.The on-wafer test results after being taped out show that the output voltage of the designed circuit is stable when the supply voltage varies from 1.6 V to 3.3 V.