一款直流偏移自校准的多模数模转换器

A Multi-Mode DAC with DC-Offset Self-Calibration

设计了一款应用于GSM/WCDMA/LTE发射机中的多模10 bit数模转换器(DAC),该DAC采用了5+5的分段式电阻型结构,达到面积和性能优化折中。通过数字可编程设计,该DAC可根据不同带宽和数据率的要求合理地控制偏置电流的大小,实现不同应用场景的低功耗目标。此外,该DAC还集成了一款改进的直流偏移自校准电路,将发射机本振泄露的抑制提高了20 dB以上。而且,直流偏移自校准在芯片上电期间完成,既不影响通道的正常工作,又不消耗额外的功耗,解决了现有的技术问题。该DAC采用0.13μm 1P4M CMOS工艺进行设计和流片,占用芯片面积小于0.1 mm^2。测试结果表明,该DAC在0.1~10 MHz的信号带宽下,具有63.0~76.8 dB的信噪失真比(SNDR)和67.9~77.9 dB的无杂散动态范围(SFDR);在1.5 V的供电电压下的最大功耗为2.2 mW。

A multi-mode 10 bit digital-to-analog converter(DAC)for GSM/WCDMA/LTE transmitter was designed.The DAC adopted a 5+5 segmented resistive architecture to achieve a good trade-off between the area and performance.In order to reduce the power consumption of the DAC in different application scenarios,the bias current of the DAC can be reasonably controlled by digital programming,according to different signal bandwidths and data rates.Moreover,by integrating an improved DC-offset self-calibration circuit,the DAC improves the local oscillation leakage suppression of the transmitter by more than 20 dB.The DC-offset self-calibration was done during the power-on sequence of the chip,which didn’t affect the normal work of the channel and didn’t consume any additional power,solving the problems of the existing techniques.The DAC was designed and implemented in a 0.13μm 1 P4 M CMOS process with an area of less than 0.1 mm^2.The test results show that it achieves a signal-to-noise and distortion ratio(SNDR)of 63.0-76.8 dB and spurious-free dynamic range(SFDR)of 67.9-77.9 dB in a 0.1-10 MHz signal bandwidth.The maximum power dissipation of the DAC is less than 2.2 mW under 1.5 V power supply.