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同时基于预知信息和预测机制的SDRAM动态页策略 被引量:1

A dynamic SDRAM page policy based on advance information and prediction mechanism
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摘要 提出一种同时基于预知信息和预测机制的SDRAM新型动态页策略。该策略可充分利用待处理访存请求的地址信息,能对后续页命中情况进行精确判断;而当没有待处理访存请求可预知时,则利用所记录的历史信息对后续页命中情况进行预测,以最大程度地选择最合适的页策略。分析证明该策略的硬件实现代价很小。实验证实三类主要的基于预知信息的动态页策略之间的性能差异较小,均能获得较理想的访存带宽,最好情况下,实际访存带宽可提升42%。其中,对于绝大多数测试激励,同时基于预知信息和预测机制的新型动态页策略的性能均为最优或接近最优,适应范围最广。 We present a novel dynamic SDRAM page policy based on prediction mechanism and ad- vance information. The policy makes full use of the addresses of memory accesses to accurately deter mine whether the next memory access is a page hit or not. If there is not a pending memory access, the policy predicts whether a page hit happens or not according to history records. Theoretical analysis shows that the policy can be easily implemented at low hardware cost. Experimental results confirm that all the three main categories of dynamic page policies based on advance information achieve the desired memory bandwidth. Under the best circumstances, the actual memory bandwidth is improved by 42 %. Among the three policies, the policy based on both prediction mechanism and advance information is the best.
作者 吕晖 谢向辉
出处 《计算机工程与科学》 CSCD 北大核心 2015年第12期2208-2215,共8页 Computer Engineering & Science
基金 国家863计划资助项目(2014AA01A301)
关键词 同步动态随机存储器 存储控制器 页打开策略 页关闭策略 动态页策略 SDRAM memory controller open page policy close page policy dynamic page policy
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  • 1Sodani A. Intel Xeon Phi processor "knights landing" archi- tectural overview[EB/OL]. E2015-11 171. http: // www. nersc, gov/assets/uploads/KNL-ISC 2015 Workshop Key note. pdf.
  • 2JohnsonDR,JohnsonMR,KelmJ H,et al. Rigel:A 1,024 core single chip accelerator architecture [J]. IEEE Micro, 2011,31(4):30 41.
  • 3Ahn J,Yoo S,Choi K. Dynamic power management ot" off chip links for hyhrid memory eubes[C]//Proc ot" the 51st ACM Annual Design Automation Conference,2014:1 6.
  • 4Park S, Park I. History-based memory mode prediction for improving memory performance[C]//Proc of the 2003 IEEE International Symposium on Circuits and Systems, 2003:185- 188.
  • 5Miura S, Ayukawa K, Watanabe T. A dynamic-SDRAM- mode-control scheme for low-power systems with a 32-bit RISC CPU[C]//Proc of the ACM 2001 International Sympo- sium on Low Power Electronics and Design,2001:358-363.
  • 6Xu Y, Agarwal A S, Davis B T. Prediction in dynamic SDRAM controller policies[C]//Proc of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling,and Simulation 2009 : 128-138.
  • 7Awasthi M, Nellans D W, Balasubamonian R, et al. Predic- tion based DRAM row-buffer management in the many-core era[C]//Proc of the llth IEEE International Conference on Parallel Architectures and Compilation Techniques, 2011: 183-184.
  • 8Xie M,Tong D,Feng Y,et al. Page policy control with mem- ory partitioning for DRAM performance and power efficiency [C]//Proc of the 2013 IEEE International Symposium on Low Power Electronics and Design,2013:298-303.
  • 9Kahn O D,Wilcox J R. Method for dynamically adjusting a memory page closing policy:U. S. Patent 6799241[P]. 2004- 9-28.
  • 10Sander B T,Madrid P E,Smaus G W. Dynamic idle counter threshold value for use in memory paging policy: U. S. Pa- tent 6976122[P]. 2005-12-13.

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