期刊文献+

一种1GHz多端口低功耗寄存器堆设计

A 1GHz multi-port low-power register file design
下载PDF
导出
摘要 超标量处理器中的寄存器堆通常采用多端口结构以支持宽发射,这种结构对寄存器堆的速度、功耗和面积提出了很大的挑战。设计了一个64*64bit多端口寄存器堆,该寄存器堆能够在同一个时钟周期内完成8次读操作和4次写操作,通过对传统单端读写结构的存储单元进行改进,提出了电源门控与位线悬空技术相结合的单端读写结构的存储单元,12个读写端口全部采用传输门以加快访问速度。采用PTM 90nm、65nm、45nm和32nm仿真模型,在Hspice上进行仿真,与传统单端读写结构相比较,所提出的方法能够显著提升寄存器堆的性能,其中写1操作延时降低超过32%,总功耗降低超过45%,而且存储单元的稳定性也得到明显改善。 Register files in superscalar processors usually adopt the multi-port structure to support the wide issue, however, this structure brings in problems such as prolonging access speed, increasing in silicon areas and higher power consumption. We design a 64 * 64 bit multi-port register file which can concurrently accomplish 8 read operations and 4 write operations in one single clock cycle. We improve the conventional single-ended memory cell structure and purpose a new structure, which combines the power-gating and the bit-line floating techniques, and the transmission gate is used in all ports to accelerate the access speed. Simulations are conducted on Hspice with PTM 90 nm, 65 nm, 45 nm and 32 nm technology models compared with the conventional single-ended structure, the proposed method can significantly improve the performance of register files, the delay of write logic 1 decreases more than 32 %, and the to- tal power consumption decreases more than 45%; the stability of memory cells is also improved.
出处 《计算机工程与科学》 CSCD 北大核心 2015年第12期2222-2227,共6页 Computer Engineering & Science
关键词 寄存器堆 单端结构 电源门控 位线悬空 register file single-ended power-gating bit-line floating
  • 相关文献

参考文献12

  • 1Patwary A R,Greub H,Feng Zhong. Bit line organization in register files for low-power and high-performance application [C]//Proc of Electrical and Computer Engineering, 2006= 505-508.
  • 2Roy S,Ranganathan N. State-retentive power gating of regis ter files in multicore processors featuring multithreaded in-or der cores[J]. Transactions on Computers, 2011,60 (11): 1547-1560.
  • 3Li Sheng-long, Li Zhao-lin, Wang Fang. Design of a high- speed low power multiport register file[C]//Proe of Micro- eletronies Electronics, 2009 : 408-411.
  • 4Wang Fang, Ji Li-jiu. Design of high speed 2Write/6Read eight-port register file[C]//Proc of 1CASIC,2003:498-501.
  • 5Sarfraz K,Chan M. A low-noise local bitline technique for dual-Vt register files[C]// Proe of Faihle Tension Faihle Consommation, 2014 : 1-4.
  • 6Gong N,Wang J, Sridhar R. Clock-biased local bit line for high performance register files[J]. Electronics Letters,2012, 48(18) :1104 1105.
  • 7Tseng J H,Asanovic K. Banked multiported register files for high-frequency supersealar microprocessors [ C] // Proc of Computer Architecture,2003 : 62-71.
  • 8Wang Dao-ping,Lin Hon-Jarn, Hwang Wei. Low-power mul- tiport SRAM with cross-point write word-lines, shared write bit-lines,and shared write row-access transistors[J]. Circuits and Systems II,2014,61(3):188-192.
  • 9Xiong Bao-yu. High performance low power multi-port regis- ter file research and full custom implementation[D]. Shang- hai:Fudan University,2011. (in Chinese).
  • 10He Peng. Full custom design and realization of large-scale multi-port high speed register File[D]. Changsha: National University of Defense Technology, 2005. (in Chinese).

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部