一种面向多核DSP芯片的低功耗验证方法

Low Power Verification Based on Multi-Cores DSP

随着芯片设计进入纳米时代,芯片的规模和工作频率不断提高,尤其在工艺发展到65nm及以下时,芯片的功耗已经成为继面积和性能之后的主要影响因素之一.面对低功耗设计技术要求的不断增加,对面向低功耗设计的仿真验证也提出了更高的要求.对此全面系统地介绍了低功耗设计的相关背景、原理和不同层次的优化技术,通过对一款多核DSP芯片的低功耗验证,针对低功耗设计的各种策略,构建了基于SystemVerilog的仿真验证环境,实现了一种高效可行的低功耗仿真验证方法.

With the IC design have developed into the nanometer era especially below 65 nm technology,the scale and the frequency of the IC are improved so that the power dissipation has become the main concern after aera and performance.For the IC design concerns with the design power increasing,the verification should be oriented the low power design.This paper presents the knowledges,principles and technologies about the low power design.For the low power technologies,this paper present a high performance and valid low power verification methodology based on SystemVerilog in a Multi-Core DSP chip.