用于3D-IC芯片间时钟同步电路的改进型SAR的设计

Design of an improved SAR for 3D-IC die-to-to clock synchronization

针对三维集成电路芯片间时钟同步电路的要求,设计一种用于全数字延时锁定环的改进型逐次逼近寄存器,以消除由于硅通孔延时波动引起的时钟偏差.采用TSMC 65 nm CMOS工艺标准单元实现改进型逐次逼近寄存器控制器,仿真结果表明其在250 MHz^2 GHz的频率范围内能有效地消除硅通孔延时波动引起的时钟偏差.

An improved successive approximation register （SAR） is designed to eliminated the clock skew caused by the through silicon vias （TSV） variation for the requirements of three-dimensional integrated circuits （3D-IC） die-to-die clock synchronization. The improved SAR is implemented using the TSMC 65 nm CMOS standard cells. The simulation results show that clock skew can be eliminated effectively between 250 MHz-2 GHz.