摘要
USB3.0帧同步电路设计的关键在于高速率下串行数据流的帧定位与数据对齐,需同时兼顾高效率和低功耗。使用Verilog HDL描述语言设计了一种基于多相位和并行检测技术的帧同步电路,重点对并行检测电路进行分析和优化。该电路在ISE中编译和仿真,结合数据进行分析,并将仿真结果进行比较验证,证明该电路能满足帧同步的速率和时序要求。
The key point of designing USB3.0 frame synchronization circuit is that frame and data alignment of serial data stream should be designed with high efficiency and low power consumption at high speed. The paper introduces a frame synchronization circuit based on multi-phase sampling and parallel detection technology designed with Verilog HDL. Our method focuses on the analysis and optimization of parallel detection circuit. The circuit is compiled and simulated in ISE. Compared with data, the simulation results show that the circuit can meet with the sneed and timing, reauirements of frame svnchronization.
出处
《微型机与应用》
2015年第24期35-37,共3页
Microcomputer & Its Applications
