基于VHDL的乘法器的设计与对比

Design and Comparison of Multiplier Based on VHDL

在数字系统中,乘法器是进行数字信号运算的核心运算单元,同时也是微处理器中进行数据处理的关键部分。以8位乘法器为例,根据简单并行乘法器、加法器树乘法器和移位相加乘法器的基本原理,利用VHDL分别进行描述和实现。对三种乘法器分别通过QuartusⅡ软件平台进行仿真,再做进一步比较和讨论。结果表明,三种乘法器在运行速度和资源占用上各有利弊,实践中可根据设计要求和硬件条件选择使用。

Multiplier is the core of digital signal calculation. It is also the key component of data processing and microprocessor. 8-bits multiplier is taken as the example. The simple parallel multiplier, the shift summation multiplier and the addition tree multiplier were introduced. They were described using VHDL. The three kinds of multipliers are simulated respectively through the Quartus II platform. Their simulation results were given. At the end of paper, the three muhipliers were compared and discussed in the resource occupancy and operation soeed.