基于FPGA的北斗导航电文译码器的研究与设计

Research and design of the navigation message decoder based on FPGA

通过对北斗导航电文BCH纠错编译码方式的深入理解和研究,提出了一种基于并行数据处理的BCH译码器的设计方案。该方案利用FPGA对BCH电文进行并行处理,在一个时钟周期内实现电文译码,提高了BCH解码模块的译码效率;同时给出了系统各个模块的Modelsim仿真结果与分析,验证了设计的可行性。本设计对提高接收机的基带数据处理性能有一定的参考和指导意义。

Through the deep understanding and researching of the BCH error correcting codes, a design scheme of BCH decoder based on parallel data processing is proposed. The scheme uses FPGA to process BCH message in parallel, can realize message decoding in one clock cycle, which improves the efficiency of decoding of BCH decoding module. Also the scheme gives each module of the system with Modelsim simulation results and analysis to verify the feasibility of the design. The design has certain reference and guiding sig- nificance for improving the receive baseband data processing performance.