多核同时多线程处理器的线程调度器设计

Design of a thread scheduler in a simultaneous multi-threaded muti-core processor

多核同时多线程处理器(SMT_PAAG)是用于图形、图像及数字信号处理的一种多核处理器。基于这种处理器提出了一种硬件线程调度器,该调度器采用同时多线程技术,最多可同时执行四个线程,支持八个线程阻塞模式下的快速上下文切换。这样避免了因阻塞带来的等待问题,能够有效提高处理器的工作效率和资源利用率。通过在处理器上运行图形处理算法进行性能评测。结果表明,SMT-PAAG处理器通过挖掘指令级并行和线程级并行,将处理器的性能提高了69.25%。

SMT-PAAG is a simultaneous multithreaded multi-core processor for graphics,image and digital signal processing.The design of hardware thread scheduler for this processor is presented here.The scheduler uses simultaneous multi-threading technology（ SMT） that can simultaneously execute up to four threads,and supports fast context switching with eight threads in blocking mode.This avoids the waiting caused by obstruction,at the same time,the design improves efficiency and resource utilization of the pro-cessor effectively.We conducted performance evaluation by running on the processor with graphics processing algorithms.The result shows that the performance of SMT-PAAG processor is increased by 69.25 % by exploring instruction level parallelism（ ILP） and tread level parallelism（ TLP）.