摘要
Memory gap has become an essential factor influencing the peak performance of high-speed CPU-based systems .To fill this gap,enlarging cache capacity has been a tradi-tional method based on static program locality principle .However,the order of instructions stored in I-Cache beore being sent to Data Processing Unit(DPU)is a king of useful infor-mation that has not ever been utilized before .So an architecture containing an Instruction Processing Unit(IPU)in paralley with the ordinary DPU is proposed,The IPU can prefetch,analyze and preprocss a large amount of instrucitons otherwise lying in the I-Calch untouched.It is more efficient than the conventional prefetch buffer that can only store several instructions for previewing.By IPU ,Load Instructions can be preprocessed while the DPU is executing on data simultaneously,It is termed as "Instrction Processed while the DPU is executing on data simultaneously.It is termed as "Instruction Processing Unit with LOokahead Cache" (IPULOC for short)in which the idea of dynamic program locality is presented.This paper describes the principle of IPULOC and illustrates the quantiative parameters for evaluation.tools for simulating the IPULOC have been developed.The simulation result shows that it can iprove program locality during program execution,and hence can improve the cache hit ratio correspondingly without further enlarging the on-chip cache that occupies a large portion of chip area.
