用高密度可编程逻辑器件实现参数化FIR滤波器

Implementation of FIR Filter Using High Density Programmable Logic Device

从提高FIR滤波器的处理速度出发 ,在传统结构的基础上导出减少乘、加次数的优化结构 ,并利用FLEX器件系列中的查找表LUT结构构成向量乘法器 ,快速完成乘、加运算 ,提高滤波器的工作速度并节省器件资源。最后 ,利用Altera公司的MAX +PLUSII软件进行了并、串FIR滤波器的逻辑设计 。

In order to accelerate the working speed of a FIR filter, the structure-optimized FIR filter, which includes a vector-multiplication that can efficiently reduce the numbers of multiplication and addition of tradition structure, has been deduced .The vector-multiplication can be realized easily by means of the LUT in HDPLD FLEX10K. Using development software of MAX+PLUS II, both parallel and serial parameteized FIR filter have been designed.