基于FPGA的低复杂度快速SIFT特征提取

Low-complexity fast SIFT feature extraction based on FPGA

尺度不变特征变换(SIFT)算法具有优良的鲁棒性,在计算机视觉领域得到广泛应用。针对SIFT算法高计算复杂度而导致其在CPU上运行实时性低的问题,基于现场可编程门阵列(FPGA)设计了一种低复杂度的快速SIFT硬件架构,主要对算法的特征描述符提取部分进行优化。通过降低梯度信息(包括梯度幅值和梯度方向)的位宽、优化高斯权重系数的产生、简化三线性插值系数的计算和简化梯度幅值直方图索引的求解等方法,避免了指数、三角函数和乘法等复杂计算,降低了硬件设计复杂度和硬件资源消耗。实验结果显示,提出的低复杂度快速SIFT硬件架构,与软件相比,可以获得约200倍的加速;与相关研究相比,速度提高了3倍,特征描述符稳定性提高了18%以上。

Scale invariant feature transform(SIFT)algorithm is widely used in the field of computer vision because of its excellent robustness.In order to solve the problem of low real-time performance of computation-intensive SIFT algorithm on CPU,a fast SIFT hardware architecture is proposed based on field programmable gate array(FPGA),with reduced complexity by optimizing the feature descriptor extraction part of the algorithm.By reducing the bit width of gradient information(including gradient amplitude and gradient direction),optimizing the generation of the Gauss weight coefficients,simplifying the calculation of the three linear interpolation coefficients and simplifying the computation process of the histogram index of the gradient amplitude,the proposed design avoids complex computations such as exponent,trigonometric function and multiplication,and reduces the complexity of hardware architecture and hardware resource consumption.The experimental results show that the proposed low-complexity fast SIFT hardware architecture can speed up by about200 times compared to the software implementation.Compared with the related research,the speed is improved by 3 times and the stability of the feature descriptor is increased by more than 18%.