基于Verilog HDL的频率计的设计

Verilog HDL-based Cymometer Design

以Altera公司Cyclone IV系列EP4CE15F17C8N器件为核心,制作了一个宽带高频小信号频率计。该系统将正弦信号通过硬件电路整形、放大、滤波后,用Verilog HDL实现分频、门控、计数、锁存、译码显示等设计,进行数据读取、运算和显示,正弦信号频率范围为1Hz-10MHz,有效值电压范围为50m V-1V,测量相对误差的绝对值不大于10-4。

Taking Chip EP2C5T144C8 of Cyclone II series from Altera as a core, a broadband high frequency small signal eymometer was designed. The sine signal will be amplified, practiced and filtered by the hardware circuit, then frequency was read, computed and displayed by Verilog HDL procedure which include the designs of door control, counting, latch, decoding display and etc. The sinusoidal signal frequency ranges from 1Hz to 10MHz, voltage from 50mV tolV, and the absolute value of relative measure error is not more than 10-4.