期刊文献+

JESD204B接口协议中的8B10B编码器设计 被引量:8

Implementation of 8B/10B Encoder Based on JESD204B Interface Protocol
下载PDF
导出
摘要 基于JESD204B接口协议设计和实现了一种新型8B10B编码器。利用极性信息简化编码码表;利用3B4B与5B6B并行编码提升电路工作频率;利用人为加入一位均衡信息,减少逻辑处理层数。仿真结果表明,电路单元面积1 756 mm2、功耗1.13 m W及最大工作频率342 m Hz,相较于传统方法具有一定的改进且完全符合JESD204B协议规范。可应用于基于JESD204B接口协议的高速串行接口的设计中。 Designed and implemented an 8B/10B encoder based on the JESD204B protocol. Polarity information simplify the coding table. The parallel encoding of 3B4B and 5B6B improves the circuit operating frequency. The use of a balanced information reduces the logical processing layers.Simulation results show that the total cell area is 1 756 μm^2,power consumption is 1.13 mW and the maximum frequency is 342 MHz. Compared with the traditional methods it has some improvements and is fully compliant with JESD204B protocol specification, and it can be ap- plied to the design of high-speed serial interface based on the JESD204B interface protocol.
出处 《电子器件》 CAS 北大核心 2015年第5期1017-1021,共5页 Chinese Journal of Electron Devices
关键词 JESD204B Serdes接口 8B10B编码器 并行编码 查找表 JESD204B serdes interface 8B 10B encoder parallel encoding lookup Table
  • 相关文献

参考文献9

  • 1J ESD204B ( l.evision of JESD204A, April 2008 ) [ S ]. Serial Inter- face fi)r Data Converters.July 2011.
  • 2李宥谋.8B/10B编码器的设计及实现[J].电讯技术,2005,45(6):26-32. 被引量:22
  • 3唐兴,唐宁.光纤通道8B/10B编码的ASIC研究与设计[J].电子器件,2011,34(2):210-214. 被引量:8
  • 4A|dullah-AI-Kafi. Develolmlent of FSM Based Running l)isparity Controlled 8b- 10b Encoder- Decoder [J]. HCTL Open lnt J of Technology hmovations and Research, 2013 ( 2 ) : 11-24.
  • 5IEEES02.3, Standard for Inflrmation technology [S]. Part 3:8B/ 10B Transmission Code. 2012.
  • 6秦蒙,王辉,秋云海,郭海涛.光纤通信中8B/10B编码器的设计与实现[J].电视技术,2014,38(1):50-54. 被引量:8
  • 7JEDECJESD204A数据转换器接口技术分析[S].恩智浦半导体.2010年4月20.
  • 8Aetel. Implementing an 8b/lOb Eneoder/l)eeoder fcr Gigabit Eth- ernet[J ]. Apploeation Nte, 1998( 10): 1-20.
  • 9Widmer A X. A DC-Balaneed, Partitioned-Bhwk, 8B/lOB Transi- mission Code [J]. IBM Journal of Research and Development, 1983 (27) : 440-451.

二级参考文献21

  • 1李宥谋.8B/10B编码器的设计及实现[J].电讯技术,2005,45(6):26-32. 被引量:22
  • 28B/10B列表[J/OL],http://www.xilinx.com/cn/bvdocs/userguides/ug035.pdf.
  • 3Widmer A X, Franaszek P A. ADC-Balance, Partitionned-Block 8B/10B Transmission Code[ J]. IBM Journal of research and development, 1983.
  • 4Samir Palnitkar.Verilog HDL数字设计与综合[M].夏宇闻,胡燕祥,刁岚松译.北京电子工业出版社,2004.
  • 5A X WIDMER,P A FRANASZEK.A DC-Balanced,Partitioned-Block,8B/ 10B Transmission Code[J].IBM J.RES.DEVELOP,1983,27(5).
  • 6CYPRESS CY7B923 HOTLINK Transmitter/ Receiver.CY7B923 HOTLink datasheet[Z].Cypress Semiconductor Corporation,2003.
  • 7Actel Corporation.Implementing an 8b/10b Encoder/Decoder for Gigabit Ethernet in the Actel SX FPGA Family[EB/OL].http://www.actel.com/documents/5192650-0.pdf,1998-10.
  • 8HAN S,LEE M S. Burst-mode penalty of AC-coupled optical receivers optimized for 8B/10B line code[J].{H}IEEE Photonics Technology Letters,2004,(07):1724-1726.doi:10.1109/LPT.2004.828362.
  • 9WIDMER A X,FRANASZEK P A. A DC-balanced,partitioned-block,8B/10B transmission code[J].{H}IBM Journal of Research and Development,1983,(05):440-451.
  • 10SHAGHAYEGH A,SARA S. A method for implementation of the DCbalanced 8B/10B coding used in superspeed USB[A].Bangalore:IEEE Computer Society,2010.68-72.

共引文献30

同被引文献36

引证文献8

二级引证文献25

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部