摘要
为了实现雷达信号处理中的脉冲压缩,同时为了适应现代雷达对灵活性的要求,设计了一种基于Virtex-5 FPGA的可动态重构的脉冲压缩系统。该系统应用局部动态重构技术,利用Xilinx公司的ISE12.2、EDK12.2、Plan Ahead12.2、System Generator12.2等相关工具,对其进行局部动态重构。结果表明,该系统将输出信号的信噪比提高了约25d B,脉冲宽度降低约40倍,并且能够实时实现不同的窗函数以适应不同环境。
In order to realize pulse compression in radar signal processing, and adapt to the flexibility required by modern radar, a pulse compression system based on Virtex-5 FPGA is designed, which can be reconfigured dynamically. Partial dynamic reconfigurable technology is applied to partially reconfigure this system, with ISE12.2, EDK12.2, PlanAheadl2.2 and System Generatorl2.2 of Xilinx Inc. The result shows that the SNR of output signal is increased by about 25dB, and the pulse width is reduced by about 40-fold. In addition, this system can realize different window function in real time to adapt to any environment.
出处
《电子器件》
CAS
北大核心
2015年第5期1070-1075,共6页
Chinese Journal of Electron Devices
基金
国家自然科学基金项目(61131004)
关键词
雷达信号处理
脉冲压缩
动态重构
FPGA
radar signal processing
pulse compression
dynamically reconfigure
FPGA
