摘要
针对高性能多核雷达信号处理芯片寄存器传输级设计调试周期长、高成本等特点,提出一套在寄存器传输级设计之前使用,基于电子系统级设计的多核建模和架构探索方法,在寄存器传输级设计前期能够进行可靠架构探索和性能分析,便于软硬件协同设计。从多核架构探索流程、数据流探索方法、具有向量处理功能的数字信号处理核/异构核的周期精度模拟器建模、多核一致性总线协议探索和总线建模及验证方案、全芯片电子系统级建模等方面论述该方法的具体实现,结合实例验证了其可行性。
Because of the long period and high-cost features of RTL design for high-performance multi-core radar signal processing chip,a multi-core modeling and architecture exploration method based on electronic system level（ESL）was proposed to provide architecture exploration and performance analysis before RTL design.The method was described in details through multicore architecture exploration process,dataflow graph method,cycle-accurate design and modeling of DSP core with vector processing,exploration method and modeling for bus and cache coherency protocol,verification and the SoC integration in ESL level.The feasibility of this method was verified through examples.
出处
《计算机工程与设计》
北大核心
2016年第1期65-70,共6页
Computer Engineering and Design
基金
核高基重大专项基金项目(2012ZX01034001-002)
