基于51核的AES算法高速硬件设计与实现

High-Speed Hardware Design and Implementation of AES Algorithm Based on 51 Core

为提高算法的效率,降低密钥运算的复杂度,提升密钥抵抗强力攻击和时间攻击能力,提出一种AES的算法方案。阐述了AES算法原理及片上系统执行AES的工作流程,基于8051软核AES算法IP原理、设计流程以及硬件模块的实现方案,并给出了效率分析及在硬件平台上的验证结果。仿真结果显示,用查表法实现AES,其IP核具有高效性,并可为密码So C产品的开发体统算法引擎支持。相比较于以往的算法模型,该方案用少量面积换取速度,大幅提高了算法的效率,因此具备良好的应用价值。

An AES algorithm scheme is proposed for higher algorithm efficiency,lower complexity of key operations and better resistance of the key against brute-force attack and time attack. The AES principles and its on-chip implementation based on 8051 soft-core are presented with workflow system and hardware modules design given. The efficiency analysis and verification results on the hardware platform are provided. Simulation results show that the AES IP core by look-up table method has high efficiency,and offers support for algorithm engine in the So C decency password product development. A substantial increase in the efficiency of the algorithm is achieved at the mere cost of a small area of the exchange rate compared with conventional algorithms.