基于IDDQ测试的VLSI门内电阻式桥接故障仿真

Simulation of Intra-gate Resistive Bridging Faults in VLSI Based on IDDQ Testing

为真实模拟集成电路中的桥接故障并评价测试集质量,提出一种基于静态电源电流(IDDQ)测试的逻辑电路门内电阻式桥接故障仿真算法.首先,针对该故障类型,提出一种覆盖率评价标准;其次,利用电路级故障注入与仿真方法构造基本逻辑门单元的故障字典;最后,通过在逻辑电路功能仿真中查询故障信息实现门级的故障仿真.仿真实验表明:相比于传统方法,所提方法能更好地反映测试集对真实桥接故障的覆盖效果,并具备良好的仿真效能.

To realistically simulate the bridging faults in VLSI and to evaluate the quality of the test set,an intra-gate non-zero resistance bridging fault simulation algorithm based on IDDQ testing was proposed.First,a fault coverage criteria was proposed for this type of fault. Second,the fault dictionary for every type of the primitive logic gate cells was constructed by using the circuit-level fault injection and simulation method. Lastly, the gate-level fault simulation was accomplished by querying the fault dictionary when performing the functional simulation of the target logic circuit. Experimental results show that,comparing with the traditional approach,the proposed method in this paper can better reflect the fault covering ability of the test set against the realistic bridging faults and the simulation is efficient.