新型低栅源漏电容射频LDMOS器件设计

The Sign of New RF LDMOS Device with Low C_(gs)

为了降低栅源寄生电容C_(gs),提出了一种带有阶梯栅n埋层结构的新型射频LDMOS器件;采用Tsuprem4软件对其进行仿真分析,重点研究了n埋层掺杂剂量和第二阶梯栅氧厚度对栅源寄生电容C_(gs)的影响,并结合传统的射频LDMOS基本结构对其进行优化设计。结果表明:这种新型结构与传统的射频LDMOS器件结构相比,使得器件的栅源寄生电容最大值降低了15.8%,截止频率提高了7.6%,且器件的阈值电压和击穿电压可以维持不变。

In order to reduce gate-source parasitic capacitance Cgs,a new RF LDMOS structure with a step gate oxideand an additional n buried layer under the gate is introduced. The Tsuprem4 tools are used for the simulation andanalysis,study is mainly focused on the influences upon Cgsfrom the doping concentration of n buried layer and thedepth of the second step gate oxide,after that,the optimization design of the device is carried out. Results show thatcomparing to conventional RF LDMOS,this new structure reduces the maximum Cgsby 15.8% and improves the cutoff frequency by 7.6%,while the threshold voltage and breakdown voltage remain unchanged at the same time.