基于混合纠错码的可容错性高速缓存研究

Fault-tolerance cache research based on mixed ECC

针对低电压下cache硬错误和软错误概率提高导致cache不能正常工作的问题,提出了一种基于混合纠错码的cache结构。该结构利用脏数据正确性必须由处理器中cache保证而干净数据可由片外恢复的数据特征,将cache分成多比特纠错码和单比特纠错码保护的两个区域。通过采用新的cache替换策略,使得脏数据总处于多比特纠错码保护区域,保证其得到较强保护,从而保证cache在低电压下的可靠性运行。基于EEMBC测试基准的实验结果表明,该设计可以在590 m V电压下正常运行,与该领域最新研究VS-ECC相比,降低了23.6%的纠错码存储信息量,性能提高5.9%。

Aiming at the problem that cache structure may fail because of the high rate of persistent and soft errors during low voltage, this paper proposed a mixed ECC based cache architecture. Based on the characteristic that clean lines were recovera- ble while dirty lines were not, it divided cache into two regions, one was protected by multi-bit ECC and the other was protec- ted by single-bit ECC. It ensured that vulnerable dirty lines were always in the region protected by multi-bit error-correcting codes through new cache replacement policy. Experiment results from EEMBC show that compared to prior work VS-ECC, this design can also work reliably at a minimum voltage of 590 mV. Furthermore, it also shows that this design reduces 23.6% of the error-correcting storage and the performance of processor improves by 5.9% averagely.