基于数字频率合成算法的硬件PWM模块设计

Hardware pulse width modulation module based on digital frequency synthesis algorithm

针对伺服电机的控制问题,对控制伺服电机的脉冲发送模块、计数模块、加减速模块进行了研究。通过分析脉冲信号产生过程,提出了一种基于FPGA的宽调频范围的脉冲产生方法。该方法采用数字频率合成算法,通过硬件描述语言Verilog HDL实现该算法的逻辑,并利用Quartus II仿真软件对所产生脉冲信号和加减计数模块进行仿真测试。在伺服电机控制平台上进行测试验证,研究结果表明该算法生成的脉冲频率可调范围为1 Hz^25 MHz,在整个脉冲段的波动不超过一个时钟周期。该脉冲发送模块具有脉冲输出均匀稳定、分辨率高、调频范围广的优点,可以满足多种伺服控制要求,为伺服电机提供稳定的控制脉冲,具有一定的应用前景。

Aiming at controlling servo motor stably , the research concerning pulse sending module , counting module and deceleration module were conducted. By analyzing the pulse signal generating process, a kind of wide tuning range of pulse generator based on FPGA was intro- duced, which is a direct digital frequency synthesis alogorithm （DDS） by using Verilog HDL hardware description language to implement the logic of the algorithm. Also the projects use Quartus II simulation software to test the pulse signal and deceleration counting module. The resuits indicate that the pulse frequency is adjustable from 1 Hz to 25 MHz, and the entire pulse period fluctuation does not exceed one clock cycle. The PWM module can be uniform and stable with high resolution and the wide range of frequency. The module can meet a variety of servo control requirements with very good prospects.