期刊文献+

基于Uppaal的实时系统AADL数据流模型的转换与验证 被引量:1

Transformation and Verification Method of AADL Data Flows for Real-time System Using Uppaal
下载PDF
导出
摘要 体系结构分析设计语言AADL是一种可支持软硬件一体化建模及同一模型多元分析的形式化与图形化建模语言。采用时间自动机形式化模型检验方法对AADL模型中的数据流进行转换和验证。考虑到单一数据流与混合数据流的差异性,分别设计了数据流到时间自动机模型的转换规则,并通过时间自动机网络实现数据流的综合分析。设计开发了自动化模型转换的插件AADLToUppaal Plug-in,将其嵌入到OSTATE工具中,使用时间自动机建模与验证工具Uppaal对转换得到的时间自动机进行模拟和验证,等价地验证所设计的AADL模型数据流时延是否满足系统实时性要求。仿真实验结果表明,所设计的数据流模型转换方法能有效地将AADL模型转换到时间自动机模型,并能在Uppaal中正确地分析原模型的数据流时延特性。 Architecture analysis and design language(AADL)is a modeling language for formalization and graphics,which can support integrated modeling and multi-analysis.We used timed automata formal checking method to transform and verify data flow in AADL models.Considering the difference between single data flow and mixed data flows,we designed corresponding transformation rules from AADL models to timed automata,and analyzed and verified the data flow comprehensively by establishing timed automata network.An automated model conversion Eclipse plug-in was designed and integrated into the AADL modeling tool OSATE.Finally,timed automata modeling and Uppaal were used to simulate and verify the transformed timed automata while verifying whether the AADL model equivalently satisfies the real-time requirement of system.Experimental results show that the model transformation method is valid and flow latency qualities can be verified effectively with Uppaal.
出处 《计算机科学》 CSCD 北大核心 2016年第1期211-217,共7页 Computer Science
基金 中央高校基本科研业务费专项资金(NS2015092)资助
关键词 AADL 时间自动机模型 数据流时延 UPPAAL 软件验证 AADL Timed automata Data flow latency Uppaal Software verification
  • 相关文献

参考文献22

  • 1Krishna C M. Real Time Systems[M]. John Wiley & Sons, Inc. , 1999.
  • 2Kleppe A G, Warmer J B, Bast W. MDA explained, the model driven architecture: Practice and promise[M]. Addison-Wesley Professional, 2003.
  • 3Feiler P H,Gluch D P, Hudak J J. The architecture analysis design language (AADL).. An introduction[R]. Carnegie-Mellon Univ Pittsburgh PA Software Engineering Inst,2006.
  • 4Feiler P H, Lewis B A, Vestal S. The SAE Architecture Analy- sis &Design Language (AADL) a standard for engineering per- formance critical systems[C]//IEEE International Symposiumon Computer Aided Control System Design. Washington: IEEE Computer Society Press, 2006 : 1206-1211.
  • 5Feller P H, Hansson J. Flow latency analysis with the architec- ture analysis and design language (aadl) :Technical Note CMU/ SEI-2007-IN-010[R]. Software Engineering, Institute, 2007.
  • 6Lee S Y, Mallet F, De Simone R. Dealing with AADL End-to- end Flow Latency with UML MARTE[C]//13th IEEE Interna- tional Conference on Engineering of Complex Computer Sys- tems, 2008(ICECCS 2008). IEEE, 2008 .. 228-233.
  • 7Jiao Ting-ting, Wang Le, Ye Guo-dong. Software Reliability Verification based on AADL[J]. Journal of Computer Applica- tion, 2012,32 (A02) : 92-95.
  • 8Peled D. Software reliability methods[M]. Springer, 2001.
  • 9Amnell T, Fersman E, Mokrushin L, et al. TIMES: a tool for schedulability analysis and code generation of real-time systems [M]. Springer Berlin Heidelberg, 2004.
  • 10Fersman E, Mokrushin L, Pettersson P, et al. Schedulability analysis of fixed-priority systems using timed automata[J]. Theo- retical Computer Science, 2006,354(2) : 301-317.

同被引文献7

引证文献1

二级引证文献7

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部