摘要
In order to overcome the bottleneck of low linearity and low resolution, an improved delay line structure is proposed with a calibration algorithm to conquer PVT （process, voltage and temperature） variations for an all- digital design. The chip is implemented in 0.13 μm CMOS technology. Measurement results show that the proposed structure with the calibration algorithm can evidently improve the linearity and resolution of the delay line. The delay resolution is 2 ps and the root mean square jitter of the delay is 4.71 ps, leading to an error vector magnitude enhancement of 1.32 dB.
In order to overcome the bottleneck of low linearity and low resolution, an improved delay line structure is proposed with a calibration algorithm to conquer PVT （process, voltage and temperature） variations for an all- digital design. The chip is implemented in 0.13 μm CMOS technology. Measurement results show that the proposed structure with the calibration algorithm can evidently improve the linearity and resolution of the delay line. The delay resolution is 2 ps and the root mean square jitter of the delay is 4.71 ps, leading to an error vector magnitude enhancement of 1.32 dB.
