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A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18μm CMOS 被引量：1

A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS
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摘要 This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter （DAC）. In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio （SNDR） of 57.5 dB and spurious-free dynamic range （SFDR） of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm2. This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter （DAC）. In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio （SNDR） of 57.5 dB and spurious-free dynamic range （SFDR） of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm2.
作者 李冬 孟桥 黎飞
机构地区 Institute of RF-&OE-ICs
出处 《Journal of Semiconductors》 EI CAS CSCD 2016年第1期106-112,共7页 半导体学报（英文版）
基金 supported by the National Natural Science Foundation of China(No.61401097)
关键词 SAR ADC switching scheme SAR control logic DAC COMPARATOR SAR ADC switching scheme SAR control logic DAC comparator
分类号 TN792 [电子电信—电路与系统]
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参考文献14

  • 1Confalonieri P, Zamprogno M, Girardi F, et al. A 2.7 mW 1 MSps 10 b analog-to-digital converter with built-in reference buffer and 1 LSB accuracy programmable input ranges. Solid-State Circuits Conference (ESSCIRC), 2004:255.
  • 2Culurciello E, Andreou A G. An 8-bit 800-μW 1.23-MSs successive approximation ADC in SOI CMOS. IEEE Trans Circuits Syst:Express Briefs, 2006, 53(9):858.
  • 3Zhu Y, Chio U F, Wei H G, et al. A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008:642.
  • 4Agnes A, Bonizzoni E, Malcovati P, et al. A 9.4-ENOB 1 V 3.8 μW 100 kS/s SAR ADC with time-domain comparator. IEEE International Solid-State Circuits Conference (ISSCC), 2008:245.
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  • 7Zhu Y, Chan C H, Chio U F, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS. IEEE J Solid-State Circuits, 2010, 45(6):1111.
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Journal of Semiconductors
2016年 第1期

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