一种软硬件协同控制的片上缓存功耗优化方法

A power optimization method of cache-on-chip with software-hardware co-control

片上多处理器系统的发展导致片上高速缓存的所占面积急剧增加,其对应的泄露功耗也相应增加。将高速缓存行划分成3部分进行控制,其中数据部分的访问分为协议访问和数据访问两部分,每部分支持多种工作模式来进行管控。通过工作模式的切换对高速缓存的三部分进行管控可以使漏过功耗平均减少76.78%,但相应的性能损失最高会达到7.74%。由于性能损失较大,提出了一种改进的高速缓存衰退的方法来优化管控策略。这种策略不仅能够把性能损失控制在3%以下,而且能够保证平均能耗优化达到近75%。

The development of on- chip multiprocessor systems leads to sharp increase in the area of on- chip cache, and its corresponding leakage power has also increased. Cache line in this article are divided into 3 parts to control while the data access section is divided into metadata access and data access in two parts, each supports a variety of modes to control. The operating mode switching to control the cache into three parts enables us to reduce leakage power consumption on average by 76. 78 %, but the loss of the performance is up to 7. 74 %. Due to the large loss of performance, this paper describes an improved method of cache decay to optimize control strategies. This strategy not only losses below 3 % performance but also ensures optimization of average en-ergy consumption to nearly 75 %.