基于FPGA的FLAC音频硬解码的设计与实现

Design and implementation of FLAC hardware decoding based on FPGA

针对高保真FLAC音频播放系统中软件解码效率低下、占用系统资源大的问题,提出一种基于FPGA的FLAC音频硬解码的设计方案。分析了FLAC音频基本编解码原理,并详细介绍了基于现场可编程门阵列(FPGA)器件的FLAC解码器各模块的设计思想和实现。利用Verilog语言在Quartus II的开发环境中进行设计输入与仿真验证。实验测试结果表明,该FLAC解码器设计灵活、工作稳定可靠、解码效率高,可作为IP核应用于不同SoC的无损音频播放系统中。

In Hi- Fi FLAC audio player system, software decoding efficiency is low, and also occupy a large number of system re-sources. To solve these problems, a design scheme of FLAC audio hard decoding based on FPGA is proposed. This paper analyze the basic principles of audio coding and decoding, and introduced the design idea and implementation of FLAC decoder based on field programmable gate array（ FPGA） device in detail. Verylog language be used to design and simulation verification in Quartus II.The experimental results show that the FLAC decoder is flexible, stable and reliable, and can be used as the IP core to be used in the SoC system.