基于关键路径的FPGA时序电路最大工作频率测试方法

Critical Path Extract Oriented Maximum Operating Frequency Testing Method for Sequential Circuit in FPGA

常规的测试时序电路最大工作频率的方法不仅受到测试设备测试能力的限制,还需要针对待测电路开发一套测试激励并逐个对待测电路进行测试,而不同的测试激励将带来测试误差.针对上述问题,提出了一种通过构建内建自测试(Build-in Self Test,BIST)电路测试FPGA中时序电路关键路径延迟,从而获取时序电路最大工作频率的测试方法.该方法根据时序电路的静态时序分析结果,首先从时序电路中抽取关键路径,随后在关键路径两端构建BIST电路并为其提供测试激励.基于该测试方法,利用C++语言开发了一个软件平台实现了对时序电路抽取关键路径和构建BIST电路的过程,大大降低了测试前构建BIST电路的时间和劳动力成本.实验结果表明,与消除了由测试激励不同带来的误差的常规方法相比,本文提出的测试方法的平均误差仅为2.70%.

The common method for testing the maximum operating frequency of sequential circuits is not only limited by the capability of the testing equipment, but it also needs to develop a suit of test patterns for the sequential circuits. The circuit under test should be tested under each pattern, however, different patterns would cause a deviation in the results. Here, a testing approach is proposed to address these problems. In the proposed testing approach, a Build-in Self-Test （BIST） circuit established to test the critical path delay of the sequential circuits in FPGA, and the maximum operating frequency is consequently achieved. According to the results of the static timing analysis, the critical path is extracted, while BIST is then established on both ends of the critical path and provides the test stimulus. A software platform automatically performing the process of extracting the critical path and establishing the BIST, is built with C＋＋ and it reduces the time and labor costs significantly. The experimental results show that the average deviation is about 2.70%, comparing to the common method with the deviation caused by different patterns removed.