摘要
本文分析介绍了几种基本乘法器的原理,它的实现基础是1-digit×1-digit乘法和多操作数加法。大多数FPGA系列包括快速实现和成本效益好的乘法器的基本元件。通过硬件描述语言分别对几种乘法器进行了FPGA设计与实现,最后从运算速度、所占用逻辑资源以及操作数长度等方面对乘法器的性能进行了分析和比较。
Multiplication is the basic arithmetic operations,its realization is based on the 1-digit × 1-digit multiplication and Multi-operand adders. Most FPGA family includes fast and cost-effective realization of the basic elements of the multiplier. This paper analyzes and introduces the principle of several basic multipliers. All of them are designed and implemented on FPGA by hardware description language. Finally,a comparisons among operation speed,logic occupied resources and operands length of the multiplier are made.
出处
《北京电子科技学院学报》
2014年第4期74-80,共7页
Journal of Beijing Electronic Science And Technology Institute
关键词
乘法器
FPGA
硬件描述语言
Multiplier
Field Programmable Gate Array
hardware description language
