基于PLL的有源环路滤波器的研究及性能分析

Based on the PLL of active loop filter's research and performance analysis

在锁相式频率合成器电路中,环路滤波器决定其电路的传输特性。当压控振荡器(VCO)的控制电压超出或非常接近电荷泵输出电压时,就需要用有源环路滤波器。文中采用ADIsim PLL V3.6软件,建立锁相环仿真模型,研究了不同阶数和拓扑结构的有源环路滤波器对锁相环(PLL)环路的影响,并对其锁相系统环路的锁定时间、频率误差、参考杂散以及相位噪声进行了详细的性能分析。对实际的工程应用提供了一定的参考价值。

In a frequency synthesizer of phase-locked circuit,its transmission characteristics of the circuit depend on the loop filter. When the VCO ＇s control voltage exceeds or is very closed to the charging pump＇s output voltage,it is needed to use active loop filter. This article adopts the ADIsim PLL V3. 6 software,based on the software the phase-locked loop simulation model is established. It describes the different order and topology structure of the active loop filter on the influence of the phase lock loop（ PLL）,and presents the detailed analysis of the performance in the PLL loop system of the lock time,frequency error,reference spur and phase noise. It provides a certain reference value for the actual engineering application.