基于FPGA的皮秒计数设计

Picosecond Counting Design Based on FPGA

在实际的现场可编程门阵列(FPGA)设计中,对纳秒以下的时间计数至今没有很好的方法进行处理。在以往的FPGA实现中,往往采用官方提供的DCM或PLL对时钟信号进行倍频处理。上述方法由于受到硬件资源的约束,用户不能随心所欲地对时钟信号进行多次处理,原因在于器件内部的DCM有限。提出了以IODELA原语为基础的方法进行时间计数设计,采用Verilog HDL硬件描述语言对皮秒进行计数操作,以Xilinx官方的Zedboard开发板和Virtex5开发板、以IODELAY原语与IDELAY原语为基础对纳秒以下的时间进行操作。经过功能仿真与板级验证,成功地实现了对于75ps^4ns(主频250 MHz的频率)的高精度计数功能。皮秒计数的实现,对于时间测量电路中细时间(主频频率<4ns的时间,即75ps^4ns的时间)的生成,以及对于进行FPGA纳秒级别以下的时钟操作产生了巨大且深远的作用。目前,该单元已经成功地应用在了时间测量电路的设计上。

In the actual FPGA design,there are not very good methods for counting under nanosecondtime.The implementation of the clock signal frequency doubling is usually used in official DCM or PLL.Due to the constraints of the hardware resources,the above method could not make the user deal with the clock signal for many times in free.The reason is that the numbers of DCM are limited in the internal device.Put forward a method to design time count based on the IODELA.Use hardware description language of Verilog HDL to count picosecond.Operate under nanosecond time based on IODELAY primitive and IDELAY primitive with Xilinx official Zedboard development board and Virtex5 development board.Propose a method of counting under nanosecond time based on primitive.Through the function simulation and board level validation,it is successful in implementation for 75 ps to 4ns（main frequency 250 MHZ frequency）of high precision counting function.Implementation of picosecond count is very important for time measurement circuit of fine time（frequency frequency under 4ns time is that time of the 75 ps to 4ns）,as well as for the FPGA nanosecond level below the clock operation.At present,the unit has been successfully used in the design of time measurement circuit.