摘要
在双相相敏检测技术的数字锁相放大器系统中,为了解决被测信号的采样频率较高造成的数字信号处理系统响应速度慢及占用硬件逻辑资源多的问题,采用多速率信号处理理论来降低被测信号的采样频率。利用级联积分梳状(CIC)滤波器实现采样率的降低,提出通过级联内插二阶多项式(ISOP)滤波器降低其通带的衰减。应用Hogenaur"剪除"理论消除来自前一级的低有效位在保证级联积分梳状滤波器滤波特性的同时减少了硬件实现时所占的逻辑资源,改进后的级联积分梳状滤波器可以获得更好的滤波性能。MATLAB与Modelsim联合仿真测试验证了设计的正确性与可行性。
In the digital lock-in amplifier system based on two-phase phase-sensitive detection technology,in order to solve the problems of corresponding slow response of the measured signal caused by the high sampling frequency and large number of hardware logical resources occupied,the multi-rate signal processing theory is used to reduce the sampling frequency. The CIC decimation filter is used to reduce the sampling frequency of the measured signal,and the cascaded ISOP filter is proposed to reducing its attenuation in the passband. The theory Hogenaur ＂cut off＂ is applied to reduce the logic resources when the CIC filter is implemented in hardware through removing low effective bits from the former level and ensured the CIC filter＇s characteristics at the same time. The improved CIC filter can get good filtering performance. Matlab and Modelsim co-simulation testing verify the correctness and feasibility of the design.
出处
《计算机仿真》
CSCD
北大核心
2016年第2期234-238,共5页
Computer Simulation
基金
湖南省自然科学基金项目资助(2015JJ6098)
南华大学重点学科建设项目资助(NHXK04)
