基于E-TSPC技术的10 GHz低功耗多模分频器的设计

Design of a 10 GHz Low-Power Multi-Modulus Frequency Divider Using E-TSPC Technique

基于扩展的真单相时钟（E-TSPC）技术,设计了一款用于10 GHz扩频时钟发生器（SSCG）的分频比范围为32~63的多模分频器（MMD）。在设计中,基于D触发器的2/3分频器采用了动态E-TSPC技术,这不仅降低了功耗和芯片面积,而且改善了最高工作频率。MMD由5级2/3分频器级联而成,由5 bit数字码控制。详细介绍和讨论了2/3分频器和MMD的工作原理和优势。MMD是SSCG的一部分,采用55 nm CMOS工艺进行了流片,芯片面积为35μm×10μm,电源电压为1.2 V,最高工作频率为10 GHz,此时功耗为1.56 m W。

Based on the extended true-single-phase-clock （E-TSPC） technique, the implementation of a multi-modulus frequency divider （MMD） was presented. The MMD is a part of a 10 GHz spread-spectrum clock generator and has a frequency dividing ratio range of 32-63. The proposed 2/3 di- vider cell based on D flip-flop adopted dynamic E-TSPC technique. This technique reduces the power consumption and chip size, and improves the maximum operating frequency. The MMD consists of a chain of five 2/3 divider cells and has a 5 bit control word. The operating principle and superiority of the proposed 2/3 divider cells and MMD were described and discussed. The chip was implemented in 55 nm CMOS process with a small area occupation （about 35μm×10μm）. The simulation results indicate a maximum operating frequency of 10 GHz and a power consumption of 1.56 mW at 1.2 V power supply.