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星载数字ASIC抗辐射加固设计与实现方法 被引量:1

Radiation-hardened Design and Implementation Methodology for Satellite Digital ASIC
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摘要 空间环境中大量带电粒子的辐射效应,特别是单粒子效应,严重威胁着空间CMOS器件的可靠性。文章首先分析了数字单粒子瞬态机理和加固技术,在此基础上,针对复杂数字ASIC电路中存在的典型结构,提出了一种适合星载复杂数字ASIC的抗辐射加固电路结构。通过对标准ASIC设计方法进行改进,给出了抗辐射加固ASIC设计流程。最后实现了一款星载ASIC的研制,流片和测试结果表明了改进的ASIC实现方法的有效性。 The radiation effects of the particles in the space environment, especially single event effects, threaten to the reliability of CMOS device. In this paper, the mechanism and hardened techniques of DSET have been analyzed firstly. Based on the analysis, a radiation-hardened circuit for the common complex digital ASIC structure was proposed, which is suitable for satellite digital ASIC design. Secondly, the standard design methodology has been improved to provide the protection of digital ASICs against the radiation environment. As a result, a radiation hardened digital ASIC for satellite application was implemented based on the improved design flow,which was shown effective by tape-outing and testing.
出处 《空间电子技术》 2015年第6期41-44,共4页 Space Electronic Technology
关键词 抗辐射加固数字ASIC 单粒子效应 单粒子瞬态 设计方法 Radiation-hardened digital ASIC Single event effect Single event transient (SET) Design methodology
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参考文献7

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二级参考文献5

  • 1Ferlet-Cavrois V, Massengill L, Gouker P. Single event transients in digital CMOS-a review [ J ]. 1EEE Transac- tions on Nuclear Science,2013,60(3) : 1767-1790.
  • 2Narasimham B, Ramachandran V, Bhuva B, et al. On-chip characterization of single event transient pulsewidths [ J ]. IEEE Transactions on Device and Materials Reliability, 2006,6(4) :542-549.
  • 3Almukhaizim S, Makris Y. Soft error mitigation through selection addition of functionally redundant wires [ J ]. IEEE Transactions on Reliability,2008,57 ( 1 ) : 23-31.
  • 4Mongkolkachit P, Bhuva B. Design technique for mitiga- tion of alpha-particle-induced single-event transients in combinational logic [ J ]. IEEE Transactions on Device and Materials Reliability,2003,3 ( 3 ) : 89 -92.
  • 5Gadlage M, Ahlbin J, Narasimham B, et al, Scaling trends in SET pulse widths in sub-100 nm bulk CMOS processes [ J]. IEEE Transactions on Nuclear Science, 2010, 57 (6) :3336-3341.

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