应力-强度干涉模型在功率半导体器件失效分析中的应用

Application of Stress-strength Interference Model in Failure Analysis of Power Semiconductor Device

功率半导体器件发生机械应力失效的直接原因是外部应力大于器件自身强度,并间接引发器件上电应力或者热应力过载,最终造成器件损坏。文章结合机械可靠性理论中应力-强度干涉模型,以晶闸管为例对其机械应力失效的物理过程和失效机理进行解释,得出失效分析和可靠性设计的工程计算方法,并结合测试中发生的晶闸管失效案例对该分析计算方法的可行性和有效性进行了验证。

The direct reason of power semiconductor device failure from mechanical stress is that outside stress comes bigger than the strength of the device, which indirectly causes upload of electricity stress or heat stress and ultimately brings about failure of the device. Combining the stress-strength interference model in mechanical reliability theory, the physical process and mechanism of thyristor failure from mechanical stress were explained by taking the thyristor as an example, and the engineering calculation in failure analysis and reliability design were obtained. Moreover, the feasibility and effectiveness of this calculation method were verified on the basis of thyristor failure case during the test.