基于CPLD的多功能数字钟的设计

Design of Multifuncton Digital Clock Based on CPLD

文中简述了一种基于CPLD的多功能数字钟的设计方案。所有电路都固化在一片CPLD芯片中,电路结构简单、控制方便,资源利用率高,成本低,调试比较容易。采用VHDL和原理图相结合的设计输入方式,在MAXPLUS II开发环境下完成设计、编译和仿真。

This article briefly introuduces a design scheme of muhifunctional digital clock based on CPLD. All circuits are cured in a CPLD chip. The circuit is simple in structure, easy to control, and has high resource utilization, low cost, which is easy to debug. The digital clock is designed,compiled as well as simulated under maxplus Ⅱ development environment, applying the design input method of the scheme combining both VHDL and block diagram together.