摘要
针对多视点视频结构复杂、带宽大小非常有限的问题,提出了基于帧处理时间模型的多视点视频解码延迟分析框架,该框架的译码器在具有多线程处理能力的多核处理器上实现。首先,假设解码延迟系统每帧在一个独立专用的处理器上被解码;然后,利用有向无环图(DGA)计算硬件解码延迟;最后,在每次迭代中,计算解码计时和解码帧的数量,定义解码时间间隔。在多视点视频实验中,对于双核处器解码计算量在60ms能得到500ms下的通信延迟值,对于四核处理器100ms解码计算量也能得到500ms下的通信延迟值。实验结果表明,一帧处理时间的上限值可以保证目标延迟值,该框架可以应用到最小通信延迟的多视点视频编码系统。
For the issue that multi-view video has more complex structure and very limited bandwidth with the needing for the decoding delay analysis system, a framework of analysis of the decoding delay in multi-view coding (MVC) is proposed. The decoder of the framework achieves on multi-core processors capabilities of multi-threaded processing. Firstly, decoding delay system assumes each frame is decoded in a separate dedicated processor. Then, a directed acyclic-graph (DGA) is used to compute hardware decoding delay. Finally, the decoding timing and the number of decoded frames are calculated, and the decoding interval is defined. In multi-view video experiments, for dual-core decoder, the calculating cost in 60ms can get the delay value under 500ms. And for a four-core processor, the calculating cost in lOOms can also obtain the delay value under 500ms. Therefore the experimental results shows that a frame the upper limit of the processing time of a frame can guarantee target delay value, and the framework can be applied to multi-view video coding system of minimum communication delay.
出处
《微型电脑应用》
2016年第2期32-35,共4页
Microcomputer Applications
基金
江苏省高校自然科学研究项目(14KJB520036)
关键词
多视点视频编码
解码延迟
多线程处理
有向无环图
Multi-view Video Coding
Decoding Delay
Multi-threaded Processing
Directed Acyclic-graph