基于存储器映射的Flash高速低功耗驱动实现

High speed and low power driver realization of Flash based on RAM mapping

针对高速大容量Flash芯片控制中面临的高速可靠性不高与动态功耗大的问题,研究了一种将复杂状态机操作映射到内嵌RAM上运行的方法。通过对内嵌RAM读地址的切换,实现了等延时的状态跳变与输出控制。同时采用加强时钟管理、分割组合逻辑来避免信号不必要的翻转,极大地提高了时序运行的可靠性并降低了其动态功耗。实践表明,该方法实现的Flash控制时序比传统的状态机在资源消耗和功耗方面均能降低50%以上,为复杂时序逻辑的实现提供了一个新思路。

Considering the reliability and power consumption problems of FPGA in modern NAND Flash chip controlling, a new design method based on FPGA internal memory mapping for finite state machine（ FSM） is proposed. In this way, transfer information and output information will be mapped to internal memory resources of FPGA, by means of controlling the address of memory to implement the state transfer of FSM, and reading data in corresponding memory address to implement state transfer information and corresponding output. The controller clock and combination of the combinational logic to avoid the unnecessary flip of signal greatly improve the reliability of working and reduce the dynamic power consumption. The practice shows that this method can reduce the resource consumption and the power consumption more than 50 % of the traditional FSM, which provides a new way in the realization of complex sequential logic.