基于PLB4总线的DDR3控制器的设计与优化

Design and Optimization of DDR3 Controller Based on PLB4 Bus

内存是计算机系统的信息存储部件,主设备与内存间信息交换的速度是影响系统性能的关键因素。PLB总线是IBM提出的嵌入式总线标准,用于主设备与片内存储以及PCIE、DMA、SRIO等高速设备的互联,在So C设计中使用广泛。该项目中DDR3作为从设备挂接到PLB4总线上,而选用的DDR3控制器IP核基于HIF接口,使用该IP核需要设计一套简单高效的总线桥逻辑,以满足系统访存性能要求。文中提出一种基于PLB4总线接口的DDR3控制器的设计方案,通过对数据流、控制流进行深入分析,采用请求合并、多级流水、数据预测、地址与控制信息复用、读数据乱序处理等方式,对访存效率影响较大的总线桥进行了速度和面积优化。仿真证明,优化后访存性能得到显著提升。

Memory is the information storage component in computer systems. The message transmission speed between the master and the memory is the key factor to affect the system performance. PLB bus put forward by IBM is a embedded bus standard,which is used for the interconnection among masters, memory and other high-speed devices like PCIE,DMA, SRIO. It is wildly used in SoC design. This project takes DDR3 as a slave connected to the PLB4 bus, which has a host interface named HIF. So an high effective cross bus bridge logic is designed to interconnect each other and improve the memory access efficiency. A DDR3 controller solution based on the PLB4 bus interface is proposed, through analysis on the data and control flow, adopting the methods of request combination, multi-pipeline, data forecast,address and control information multiplexing,data reading out of order processing to optimize speed and size of the bridge logic which will influence the memory access delay. Simulation proves that after optimization the performance has been improved remarkably.