高速时钟驱动电路的优化设计

Design Optimization of High-speed Clock Drive Circuit

随着系统电路工作频率的不断提高,在应用中对系统互连和电路间的时钟传输提出了更高的要求。提出了一款基于LVDS(低压差分信号)接口的时钟分路驱动电路,该电路可输出四路时钟信号,工作频率在2 GHz以下,电路采用了0.13μm CMOS工艺,电源电压为3.3 V,内部集成了LDO电路。主要阐述了如何通过内部预加重电路,共模电压稳定电路,占空比调整电路等模块来优化电路的性能,并配合仿真进行了相关的分析。

Owing to the increasing high frequency of circuit systems,it is required to improve the performance of clock signal transmission,applying to system interconnection and circuit. The paper presents a multi-channel clock drive module,based on Low-Voltage Differential Signaling（ LVDS） interface. Having four clock signal outputs,the LVDS interface is designed in 0. 13 μm CMOS process and is supplied in 3. 3V supply source. It works in highest frequency of 2GHz and consists an inter LDO module. Also,this paper presents how to optimize circuit features,using internal pre-emphasis module,common mode stabilizer and duty cycle corrector. Finally,analysis is put forward in virtue of simulation.