摘要
提出一种适合心电信号检测的低压、低功耗、低噪声、高共模抑制比的差分差值斩波前置放大器,包括偏置电路、主放大电路和时钟产生电路,其中,时钟产生电路包括张弛振荡器和两相非交叠时钟产生电路。该放大器采用斩波技术减小了低频1/f噪声,采用差分差值输入、交叉耦合结构增加了共模抑制比,采用T型电容反馈减小了芯片面积,优化了放大器性能。芯片采用SMIC0.18μm 1P6M CMOS工艺设计,使用PSS,PAC,PNOISE进行仿真分析。结果表明,放大器在1.8V电源电压下,静态电流为35μA,闭环增益为40.6dB,共模抑制比为115dB,输入等效噪声仅为950nV(rms)(0.01~100Hz),适用于心电信号检测领域。
A low-voltage low-power low-noise and high common-mode rejection ratio(CMRR)chopper stabilized differential difference preamplifier was presented for electrocardiogram(ECG)signal acquisition.The proposed circuit contained a bias circuit,a main amplifier and a clock generation circuit,and the clock circuit contained a relaxation oscillator and a non-overlapping clock generator.Chopper stabilized technique was used to reduce the 1/f noise at low frequency.Differential difference input and cross-coupling were used to get high CMRR.T-network capacitor feedback was used to reduce chip area.So the amplifiers performances had been optimized.This circuit was designed in SMIC 0.18μm 1P6 M CMOS process,and was simulated with PSS,PAC,PNOISE.The results showed that the amplifier consumed a total current of only 35μA with a supply voltage of 1.8V,and achieved an AC gain of 40.6dB,a high CMRR of 115 dB,a low input referred noise of 950nV(rms)from 0.01 Hz to 100 Hz.It could be an attractive candidate for ECG signal acquisition.
出处
《微电子学》
CAS
CSCD
北大核心
2016年第1期29-33,共5页
Microelectronics
基金
国家自然科学基金资助项目(61161003
61264001
61166004)
广西自然科学基金资助项目(2013GXNSFAA019333)
关键词
心电信号
斩波技术
差分差值放大器
ECG signal
Chopper stabilized technique
Differential difference amplifier