SAR ADC移位寄存方式的优化

Improvement of the Control Circuit for SAR ADC

逐次逼近型模数转换器主要由电容阵列、比较器和数字控制电路组成。传统的数字控制电路保存一位数据时,需要依次经过移位和锁存两个步骤,因此每位数据的延迟约为两个D触发器的延迟时间,制约了转换速度。通过优化数字控制电路的移位寄存方式,使移位和寄存两个步骤只间隔一个与门的延迟时间,每次移位寄存的总延迟降低为一个D触发器和一个与门的延时之和,提高了转换速度。仿真分析表明,改进的逻辑结构延迟较传统结构降低了约28%。

The successive approximation ADC is mainly composed of DAC,the comparator and logic control module.In the traditional control circuit structure,the output signal of comparator is shifted by a D flip-flop,and registered by another D flip-flop.So the delay time of one bit is about 2 Dt（the delay of one D flip-flip）.The proposed control circuit only consumed Dt and Dand（the delay of one ＂and＂gate）,because of the difference of triggered methods.The simulation results showed that the improved structure achieved 28%reduction of delay time compared with the traditional structure.