一种基于FPGA的时钟相移时间数字转换器

A FPGA-Based Time-to-Digital Converter with Shifted Clock Sampling Technique

提出了一种基于Xilinx Virtex-5FPGA的时钟相移采样(SCS)时间数字转换器(TDC)。利用Virtex5内部的时钟管理模块(CMT)产生16路固定相移的时钟信号,经过16路D触发器对输入信号同时进行采样量化。与传统的基于抽头延迟链结构相比,所用资源更少,性能更加稳定。仿真结果表明,该TDC的精度高于64ps,占用数字时钟管理(DCM)与锁相环(PLL)资源小于20%,积分非线性(INL)和微分非线性(DNL)都小于0.3LSB。

A kind of time-to-digital converter（TDC）was designed with shifted clock sampling technique in Xilinxs general purpose Virtex-5field programmable gate array（FPGA）.The clock management tile（CMT）was utilized to produce 16-channel fixed phase-shifted signals,then was combined with 16D-type flip-flops to sample and quantify the input signal.Compared with the traditional TDC design methods,such as tapped delay lines,the proposed circuit needed lower resources,and was more stable.The simulation results showed that the time accuracy was as high as 64 ps,and less than 20% of DCM and PLL resources in FPGA were used.The integral nonlinearity（INL）and differential nonlinearity（DNL）characteristics of the designed TDC were both less than 0.3LSB.