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一种6.25Gb/s带预加重结构的低压差分发送器

A 6.25Gb/s Low Voltage Differential Signal Transmitter with Pre-Emphasis
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摘要 采用SMIC 40nm CMOS工艺,设计了一种带预加重结构的低压差分(LVDS)发送器。低压差分驱动器采用双运放反馈控制电路,可稳定输出信号的摆幅。采用边沿检测电流注入的预加重电路,对输出进行高频预加重,克服了数据高速传输中高频信号的损失。该发送器的速率为6.25Gb/s,输出差分信号摆幅为300mV,预加重比例为3.5dB,功耗为7.1mW。该低压差分发送器可应用于高速IO物理层电路中。 A 6.25Gb/s low voltage differential signal（LVDS）transmitter with pre-emphasis was designed based on SMIC 40 nm CMOS technology.The low voltage differential driver used dual op amp closed-loop feedback control structure to stabilize the swing of output signal.The pre-emphasis circuit used pulse-current boosting structure,which emphasized output signal to overcome high frequency signal loss during transmission.This transmitter could output a low voltage differential signal with the swing of 300 mV and the rate of 6.25Gb/s.The pre-emphasis radio was 3.5dB.The power consumption was 7.1mW.This transmitter was applicable for rapid IO PHY circuit.
作者 陈浩 黄鲁 张步青
机构地区 中国科学技术大学电子科学与技术系 中国科学院自动化研究所
出处 《微电子学》 CAS CSCD 北大核心 2016年第1期67-70,共4页 Microelectronics
基金 中科院A类战略性先导科技专项资助项目"面向感知中国的新一代信息技术研究"(XDA06010402)
关键词 并串转换 预加重 低压差分发送器 高速IO Parallel to serial conversion Pre-emphasis Low voltage differential signal transmitter Rapid IO
分类号 TN432 [电子电信—微电子学与固体电子学]
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参考文献6

  • 1韦雪明,李平.一种2.5Gb/s带预加重结构的低压差分串行发送器[J].微电子学,2010,40(6):770-773. 被引量：4
  • 2BULZACCHELLI J F, MEGHELLI M, RYLOV S V, et al. A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology [J]. IEEE J Sol Sta Circ, 2006. 41(12): 2885-2900.
  • 3CHEN S, LI H, SHI X B, et al. A low-power high- swing voltage-mode transmitter [J]. J Semicond, 2012, 33(4) : 045003-1 - 045003-6.
  • 4黄林,郭淦,叶菁华,陈一辉,洪志良.一种采用半速结构的CMOS串行数据收发器的设计[J].Journal of Semiconductors,2005,26(1):180-186. 被引量：2
  • 5POULTON J, PALMER R, FULLER A M, et al. A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS[J]. IEEE J Sol Sta Circ, 2007, 42(12): 2745-2757.
  • 6FUKUDA K, YAMASHITA H, ONO G, et al. A 12.3-mW 12.5-Gb/s complete transceiver in 65-nm CMOS process [J]. IEEE J Sol Sta Circ, 2010, 45 (12) :2838-2849.

二级参考文献14

  • 1张家川,刘伯安.高速多电平LVDS收发器设计[J].微电子学与计算机,2007,24(4):69-71. 被引量：8
  • 2IEEE standard for low voltage differential signals(LVDS) for scalable coherent interface[S]. IEEE Std 1596. 3- 1996, 1996.
  • 3ZHAO Zhenyu, WANG Jianjun, LI Shaoqing, et al. A 2. 5-Gb/s 0. 13um CMOS current mode logic transceiver with pre-emphasis and equalization [C] // 7th Int Conf ASIC. Guilin,China. 2007. 368-371.
  • 4PAUL W,DICKSON T O,VOINIGESCU S P. A 1.5 V 20/30 Gbps CMOS backplane driver with digital preemphasis[C] // Proc IEEE Cust Integr Circ Conf. Orlando,Florida,USA. 2004: 23-26.
  • 5CHOI S W, LEE H B, PARK H J. A three-data differential signaling over four conductors with pre-emphasis "and equalization: a CMOS current mode implementation [J]. IEEE J Sol Sta Circ, 2006, 41 (3) : 633-641.
  • 6Maneatis J G,Horowitz M A.Precise delay generation using coupled oscillators.IEEE J Solid-State Circuits,1993,28(12):1273.
  • 7Maneatis J G.Low-jitter process-independent DLL and PLL based on self-biased techniques.IEEE J Solid-State Circuits,1996,31(11):1723.
  • 8De Vito L M.A versatile clock recovery architecture andmonolithic implementation.In:Monolithic phase-locked loops and clock recovery circuits.New York:IEEE Press,1996:405.
  • 9Lee K,Kim S,Ahn G,et al.A CMOS serial link for fully du- plexed data communication.IEEE J Solid-State Circuits,1995,30(4):353?A
  • 10Rau M,Oberst T,Lares A,et al.Clock/data recovery PLL using half-frequency clock.IEEE J Solid-State Circuits,1997,32(7):1156.

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