一种片内信号间的相位检测与同步电路

A Phase Detection and Synchronization Circuit for On-Chip Signals

提出了一种片内信号间的相位检测与同步电路。该电路通过检测信号间的相位信息,连续调整其中一个信号的延迟,从而保持信号与信号之间始终处于设定的相位同步关系。介绍了相位检测与同步电路的原理及结构,给出了每一个模块的具体电路结构并加以分析。基于SMIC 65nm CMOS工艺,采用Cadence Spectre进行仿真,结果表明,电路可产生16个固定的相位关系,工作在1~4GHz的宽频范围,在4GHz工作频率时功耗为52mW,而芯片尺寸为450μm×450μm。

An on-chip signal phase detection and synchronization circuit was presented.The circuit received phase relational information and continuously adjusted the delay line to maintain the desired phase relationships between the on-chip signals.The architecture and principle of the circuit was analyzed,and the designs of all blocks of the circuit were described in detail.The proposed phase detection and synchronization circuit was designed in SMIC 65 nm CMOS technology and Cadence Spectre simulator.Simulation results showed that it could generate 16 fixed phase relationships and operate over a wide frequency range from 1GHz to 4GHz.It consumed 52 mW at 4GHz.The chip active size was 450μm×450μm.