一种适用于任意余数基的高性能后向转换结构

An Efficient Architecture of Reverse Converter for Arbitrary Moduli Set

后向转换是从余数到二进制数的转换,在余数系统的应用中既是重点也是难点。通过简化中国剩余定理,避免对M求模,提出了一种适用于任意余数基的高性能后向转换结构。该结构采用Verilog HDL进行代码设计,并用VCS和Verdi进行仿真和验证,最后选择SMIC 0.13μm工艺并采用DC工具完成代码综合,生成面积和时延报告。综合结果表明,该结构的"面积×时延"复杂度较同类的中国剩余定理结构和混合基转换结构,分别降低了23.3%和26.4%,转换性能显著提高。

The conversion from residue to the binary number which is often called reverse conversion,is critical and difficult for the practicality of residue number system（RNS）.By simplifying the Chinese remainder theorem（CRT）and avoiding modulo M,an efficient architecture of reverse converter for the arbitrary moduli set was proposed.Its code design was accomplished in Verilog HDL.VCS and Verdi were employed to complete the simulation and verification.Finally,Design Compiler with SMIC 0.13μm technology was used to synthesize the RTL codes and generate the reports of area and delay as well.Compared with the CRT-based architecture and the MRC-based architecture,the synthesized results indicated that the proposed architecture could achieve an average complexity of ＂area×delay＂savings of 23.3% and 26.4% respectively,and the conversion performance was improved significantly.