摘要
随着社会的不断发展,在信息和数据传输等方面,人们的需求不断增长,因而对于通信系统的要求越来越高。在高速通信系统当中,为了提高系统的传输效率和传输安全,采用了很多相关的技术手段来对系统进行完善。其中,RS编解码是通信系统中一项十分重要的技术,本文设计的通信系统中采用RS编码,并且在FPGA上对RS编译码器进行了仿真与分析,以期为其日后的发展提供借鉴。
With the continuous development of society, people＇s demand is growing in the information and data transmission, etc. rhus the requirement of communication system becomes more and more highly. In the high speed communication system, in order to improve the transmission efficiency and transmission of system security, USES a lot of related technical measures to improve the system. Among them, the RS decoding communication system is a very important technology. In this paper, the design of the communication system using RS encoding, and the RS compiler code simulation and analysis based on the FPGA, so as to provide reference for its future development.
出处
《电子测试》
2015年第12期57-59,63,共4页
Electronic Test
关键词
高速数字通信
纠错
RS编译码
FPGA
high speed digital communication
Error correction
RS encoding decoding
FPGA
