PFA在FPGA正则引擎上的设计和仿真

Design and Simulation of FPGA Engine for Regular Expressions Matching Based on PFA

将后缀自动机构造方法应用到现场可编程门阵列的正则引擎设计上,能够有效地压缩状态空间,提高"速度"和"面积"这2个最主要的现场可编程门阵列的引擎性能指标,并能利用有限的现场可编程门阵列资源来实现更多正则表达式的匹配处理.Testbench模拟仿真结果表明,所设计的正则引擎完全实现了预期匹配要求,而其支持的正则表达式的数量和匹配速度都因有效的规模压缩而得到了很大的提升,对比传统的基于Thompson不确定的有限自动机实现的硬件引擎,其所需要的硬件逻辑资源更少,能够并行执行的正则表达式数量也就越多,提高了匹配效率.

A field programmable gate array（ FPGA） engine for regular expressions matching based on postfix automata（ PFA） was designed. PFA can obtain smaller size and then reduce the space effectively.The limited FPGA resources can be used to implement more regular expressions simultaneously. Simulation by Testbench implies that the number and speed of the supported regular expressions is deeply improved. Compared with Thompson non-deterministic finite automata（ NFA） method,it needs less hardware resources and the number of regular expressions that can be implemented concurrently becomes more,so the efficiency of implement has been increased.